Electronic integrated circuits, or “chips” have become significantly more complex as circuit fabrication technologies have improved. It is not uncommon for integrated circuits to incorporate hundreds of millions of transistors, with a comparable number of interconnects, or signal paths, integrated together onto a single piece of silicon substrate no larger than the size of a coin. In addition, often the same functionality that once required multiple chips can now be integrated onto the same chip, a concept often referred to as “system-on-chip” technology.
The design of integrated circuits has likewise become more difficult as complexity has increased. Whereas early chips were often designed gate by gate, more advanced integrated circuits incorporating millions of gates represent too much of an undertaking for early design methodologies. Likewise, another important aspect of integrated circuit design is that of testing and verifying an integrated circuit design, both from the standpoint of verifying that a design will logically operate as intended, and of ensuring that a design will comply with the physical limitations that are inherent in any integrated circuit, i.e., to ensure that all timing and delay constraints are met.
As a result, a variety of software design applications, or tools, have been developed to assist designers with designing and testing integrated circuits.
Generally when utilizing these tools, the overall design process is represented by two stages. The first stage is referred to as logic design, where the desired functional operation of an integrated circuit is initially defined and tested. The second stage is referred to as physical design, where the logic design created during the logic design stage is processed to select actual circuit components to implement the functions defined in the logic design, and to lay out the components on an integrated circuit and route interconnects therebetween. The interconnections between circuit elements are often referred to as nets, and the nets are generally routed after placement of circuit components at specific locations on an integrated circuit.
Often, automated design tools rely on standardized circuit components, referred to as logic cells, which are self-contained, reusable and pre-tested circuit designs that represent specific higher level functions. Logic cells simplify a number of design steps. For example, logic design is simplified given that the logic synthesis tool is able to construct a circuit from fewer, more complex functions. Furthermore, both physical design and verification are often simplified because the logic cells function more or less like a “black box”, whereas all of the individual gates and interconnects in a logic cell have already been placed relative to one another and tested beforehand.
In addition, some logic cells may be configured to provide different logical responses depending upon how they are interconnected with other circuit components. For example, a logic cell might be utilized to provide a generalized function such as A AND B AND C AND D AND E, where A-E are different inputs. Should one particular design only need to implement the function A AND B AND C, the D and E inputs could simply be connected to a logic 1 value to effectively remove those inputs from the function. Likewise, where only a function such as A AND B be needed in a different design, the C, D and E inputs could be connected to a logic 1 value, resulting in the same logic cell having a different logical response than in the first example.
Conventional logic design using logic cells, however, suffers from a number of drawbacks. Often the logic cells differ in size and shape, which can lead to inefficient space utilization when placed in a design. Furthermore, routing of the interconnects and clock signals is often haphazard and irregular, in many instances creating timing problems such as skew and jitter that require excessive testing and redesign.
In addition, conventional design methodologies and tools have typically been limited to use with logic cells implemented using static logic. More recently, however, dynamic logic has come into favor in circuit designs due to faster speed, lower power consumption, and reduced gate count. With dynamic logic, a clock signal is used to precondition a circuit of gates to a steady state during a precharge phase of the clock, then during an evaluate phase of the clock, a boolean function of the inputs of the circuit is evaluated and output by the circuit.
Logic synthesis tools have conventionally been unable to effectively utilize dynamic logic due in part to tighter stricter timing constraints associated with dynamic logic. In many cases, automated routing of the clock and interconnect signals is simply too irregular to meet the strict timing requirements of dynamic circuits.
Yet another drawback of conventional design methodologies arises when changes in the logic design a required at later stages of the development cycle. Oftentimes, dummy cells may be incorporated into a design to account for the possibility that the logic functions to be implemented in a circuit will be changed at a later point in the design process. If such dummy cells are never utilized, however, the space allocated to the dummy cell is effectively wasted, thus increasing the size and overall cost of the design.
Therefore, a significant need continues to exist for a circuit design methodology that supports the use of dynamic logic in a circuit design, as well as reduces the irregularities and inefficiencies associated with conventional methodologies and tools.